Computer Architecture - ARM Instruction Format
Data-processing
cond
op = 00
funct
I
I = 0: Src2 is a register
I = 1: Src2 is an immediate
cmd
S
- S = 1: instruction sets condition flags
Immediate Src2
<OP Rd, Rn, #Imm8_rot>
Imm8: 8-bit unsigned immediate
rot: 4-bit rotation value
Register Src2
<OP Rd, Rn, Rm, ST #shamt5>
Rm: the second source operand
shamt5: the amount Rm is shifted
sh: the type of shift
Register-shifted Register Src2
<OP Rd, Rn, Rm, ST Rs>
类似于 Register Src2,其中的 shamt5 被 Rs 代替。
Memory
op = 01
funct
I: immediate bar
P: preindex
U: add
B: byte
W: writeback
L: load
Rn: base register
Rd: destination (load), source (store)
Src2: offset
Immediate
<OP Rd, [Rn, #Imm12]>
Register
<OP Rd, [Rn, Rm, ST #shamt5]>
Branch
op = 10
funct = 1L
L = 1: BL
L = 0: B
Imm24: 24-bit immediate encoding Branch Target Address (BTA)
评论